Daniel Ng

2nd Year Electrical Engineering @ UBC

Working at the hardware–software boundary: FPGA CPUs, embedded firmware, and system-level verification.

Hardware Intern

Norsat International

RF characterization and hardware testing for satellite communication systems

VNARF CharacterizationSMT/THTPCB Rework
  • Characterized Ku-Band Block-Up Converters (gain, Psat, P1dB, spurious, IMD3, noise figure) using VNAs, signal analyzers, oscilloscopes, and multimeters to ensure 100% compliance with hardware specifications.
  • Optimized RF power module stability by precisely sweeping DAC control codes, significantly reducing variance in output power prior to final acceptance testing.
  • Assembled and troubleshot BUCs and LNBs at the PCBA level, performing microscopic SMT and THT soldering and inspection to maintain quality standards for high-sensitivity MMIC chips.
  • Verified and troubleshot SSPA boards by conducting continuity tests and cross-referencing schematics to identify and rectify DC bias instability, ensuring 100% yield for high-power MMIC stages.

Laser Timing Gates

Formula UBC Racing

End-to-end development of 650 nm laser gate receivers with ESP32-S3 MCUs

Altium DesignerEmbedded CESP32-S3Analog Design
GitHub
  • Led end-to-end development of a laser receiver, including optomechanical shrouding coupled with a custom 3.3V CMOS analog front end and 2.4GHz communication between master-slave ESP32-S3 MCUs to calculate speed and lap times.
  • Characterized baseline photodiode thermal dark current and TIA voltage noise to calibrate an adjustable hysteresis threshold via potentiometer, targeting a 20dB SNR and BER < 10−7 to ensure high-speed data integrity.

Interrupt-Driven Alarm Clock

Academic Project

Real-time settable clock using 16.6 MHz oscillator with timer-driven interrupts

A51 AssemblyN76E003InterruptsLCD
GitHub
  • Engineered a real-time settable clock using a 16.6 MHz oscillator to drive timers and interrupts.
  • Utilized Timer 0 to generate a stable 2 kHz square wave for audio signaling and Timer 2 to manage high-precision half-second BCD clock increments.
  • Interfaced a 4-bit LCD for time/alarm display and implemented a sampling-based debouncing algorithm coupled with decoupling capacitors for pushbutton inputs to eliminate noise.

Temperature Telemetry System

Academic Project

High-precision temperature sensing with RS-232 telemetry and real-time visualization

PythonCA51 AssemblyADCRS-232
GitHub
  • Designed a high-precision analog front-end by interfacing an LM335 sensor with a 12-bit SAR ADC, utilizing an LM4040 external voltage reference (VREF=4.096V) to eliminate measurement instability inherent in internal band-gap references.
  • Engineered a 32-bit assembly math library to execute voltage-to-temperature transfer functions via integer-scaling, enabling 115.2 kbps telemetry transmission via RS-232 to a custom Python suite for real-time data visualization.

RISC-V Single Cycle CPU

Academic Project

Single-cycle RISC-V processor with assertion-based verification on Altera FPGA

SystemVerilogAltera FPGAQuartus PrimeQuesta
GitHub
  • Architected and implemented a single-cycle RISC-V processor in SystemVerilog with MMIO on Altera's DE10-Lite with functioning register file, ALU, and control unit, supporting a 10-instruction subset of the RISC-V ISA.
  • Wrote a self-checking non-synthesizable testbench with assertion-based verification to verify instruction-level correctness and used Questa to trace signals through the synchronous timing datapath.

Tron Light Cycle Game

Academic Project

Custom VGA driver with interrupt-driven controls and autonomous opponent AI

Embedded CMMIOVGA DriverISR
GitHub
  • Developed a custom VGA graphics driver using Memory-Mapped I/O (MMIO) to manage frame buffers, rendering dynamic light traces and maintaining real-time pixel updates at VGA timing constraints.
  • Implemented interrupt-driven input handling via an ISR to handle asynchronous pushbutton events, reducing input latency compared to traditional polling.
  • Engineered an autonomous robot opponent with predictive collision logic, performing real-time memory reads of the VGA buffer to scan for obstacles and update movement vectors.

Reflow Oven Controller

In Progress

Closed-loop thermal control using thermocouple feedback and PWM power regulation

Embedded CPWMPID ControlSPI
  • ⏳ Work in progress — check back mid-February!

Autonomous Field-Following Robot

In Progress

Mobile robot with magnetic field detection and collision avoidance

State MachinesMagnetic SensorsH-BridgeSTM32
  • ⏳ Work in progress — check back early April!

Skills

Digital Design / HDL

SystemVerilogRISC-V AssemblyA51 AssemblyFSM DesignCPU Architecture

Embedded Systems

ESP32-S38051 MCUsEmbedded CSPI / UART / I2CBare Metal

Design Tools

Quartus PrimeQuesta / ModelSimAltium DesignerCPUlator

Hardware & Lab

VNASignal AnalyzerPCB DesignSMT/THT SolderingOscilloscope

Currently Learning

SystemVerilog & UVM

Refining testbench development and researching UVM for professional-scale verification workflows.

Timing & Clocking

Studying Clock Domain Crossing, PLLs, and TCL/Python automation for high-speed design.

CAN Bus

Learning how our UBC Formula car communicates telemetry and ECU data over a single robust bus.

GPU & AI Hardware

Comparing traditional GPU architectures with DSAs like TPUs for modern AI inference workloads.

Contact

Open to co-op opportunities starting May 2026. Let's have a coffee chat.