Inspired by Altium Designer
L1 · Top Overlay

Hi, I'm Daniel.
I design useful hardware and firmware.

Electrical Engineering at UBC. I lay out mixed-signal boards and write the bare-metal C and FreeRTOS firmware that runs on them.

Available January 2027 Incoming HW Engineering Intern · Ciena
Electrical Engineering (BASc) · UBC Vancouver, Canada
L2 · Top Copper

Formula UBC: Laser Timing Gates

A pair of laser gates for the FSAE test track. They sync their clocks over the air, so a lap time holds up to under a millisecond.

  • ESP32-C3 gates synchronised over ESP-NOW, no access point required.
  • Photodiode transimpedance front end with comparator threshold and ambient rejection.
  • LiPo PowerPath + charge management for all-day paddock use.
ESP32-C3ESP-NOWTIALiPo PowerPath
Open project
L3 · Signal 1

PoE Dev Board

A powered-device board that takes its supply and its 10/100 Ethernet off the same RJ45 cable.

  • Isolated 802.3af powered-device front end with flyback conversion.
  • W5500 hardwired TCP/IP MAC+PHY driven over SPI from an ESP32.
  • Isolation barrier, magnetics and creepage handled at layout time.
ESP32W5500802.3afIsolated PD
Open project
L4 · Bottom Copper

Line Follower Wireless Remote

A hand-built IR controller for a line-following robot, from carrier generation up to the protocol.

  • EFM8 8-bit core bit-banging a 38 kHz NEC carrier out of a timer.
  • Mixed-signal board: keypad matrix, driver stage, regulation on one 2-layer PCB.
  • Full schematic capture and layout in Altium Designer.
EFM8NEC IRAltiumMixed-signal
Open project
L5 · Bottom Overlay

Bare-Metal Digital Multimeter

A multimeter whose firmware is written straight against the STM32L051 reference manual, without a HAL.

  • STM32L051 firmware at register level: ADC, timers, clock tree, all by hand.
  • Resistance, capacitance and inductance modes from one analog front end.
  • Written to the BARR-C:2018 embedded coding standard.
STM32L051Register-level CBARR-CR/C/L
Open project
02 / Assembly notes

Experience

Ciena

WaveLogic Modem HW Engineering Intern

Ciena · Ottawa, ON
Sept 2026 – Dec 2026
Coherent OpticsModem Hardware

Incoming Fall 2026 co-op on the WaveLogic coherent optical modem hardware team.

Norsat International

Electrical Engineering Intern

Norsat International
May 2026 – July 2026
LabVIEWPythonPyVISAGPIBSCPILTspice
  • RF debug: traced unwanted PLL spurs by decoding the SPI register writes against the datasheet bit fields, then checked divider settings, PFD frequency, spur spacing and integer-boundary risk.
  • Bias-tee verification: reviewed 50 Ω and 75 Ω networks at circuit level. Worked out impedance, insertion loss and return loss, then picked the VNA validation points off the SPICE estimates.
  • Rework validation: wrote test recommendations for the bias-tee PCB rework variants. The risks I flagged were shunt-loss paths, impedance matching and GHz parasitics.
  • ATE modernization: reverse-engineered the legacy LabVIEW workflows into a Python/PyVISA layout that keeps instrument control, test sequencing, calibration and reporting in separate modules.
Norsat International

Hardware Test Intern

Norsat International
June 2025 – August 2025
PNA-X VNASignal AnalyzersOscilloscopesSMT/THT Rework
  • RF characterization: validated block-up converter gain, output power, saturation and spurious parameters against product specs using PNA-X VNAs and signal analyzers.
  • Rework & assembly: microscope-assisted SMT/THT soldering, rework and inspection on BUC/LNB hardware.
03 / Bill of materials

Toolchain

04 / Off the bench

Chess

daniel_whn // Rapid 1112 // Blitz 937 // Bullet 1015 // Puzzles 1732 peak
daniel_whn vs ruzicarosi Loss // Bullet // May 18
daniel_whn vs kuzeyalkanm Draw // Bullet // May 18
daniel_whn vs CORPSEJADED Loss // Bullet // May 18